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Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADM1170-1AUJ
ADM1170-2AUJ
ADM1170
TIMER 1
8
V CC
TIMER 1
8
V CC
GND 2
TOP VIEW
7
SENSE+
GND 2
TOP VIEW
7
SENSE+
SS 3 (Not to Scale) 6 SENSE–
SS 3 (Not to Scale) 6 SENSE–
ON 4
5
GATE
ON-CLR 4
5
GATE
Figure 2. Pin Configuration, 1AUJ Model
Table 4. Pin Function Descriptions
Figure 3. Pin Configuration, 2AUJ Model
Pin No.
1
2
3
4
5
6, 7
8
Mnemonic
TIMER
GND
SS
ON (ON-CLR)
GATE
SENSE?, SENSE+
V CC
Description
Timer Input Pin. The initial and circuit breaker timing cycles are set by this external capacitor. The initial timing
delay is 272.9 ms/μF, and 21.7 ms/μF for a circuit breaker delay. When the TIMER pin is pulled beyond the
upper threshold, the GATE turns off.
Chip Ground Pin.
Soft Start Pin. An external capacitor between the SS pin and GND sets the ramp rate of the current limit
reference.
Input Pin. The ON (ON-CLR) pin is an input to a comparator that has a low-to-high threshold of 1.3 V with
80 mV hysteresis and a glitch filter. The ADM1170 is reset when the ON (ON-CLR) pin is low. When the ON
(ON-CLR) pin is high, the ADM1170 is enabled. A rising edge on this pin has the added function of clearing a
Gate Output Pin. An internal charge pump provides a 12 μA pull-up current to drive the gate of an N-channel
MOSFET. In an overcurrent condition, the ADM1170 controls the external FET to maintain a constant load
current.
Current Limit Sense Input Pins. The current limit is set via a sense resistor between the SENSE+ and SENSE?
pins. In an overcurrent condition, the gate of the FET is controlled to maintain the SENSE voltage at 50 mV.
When this limit is reached, the TIMER circuit breaker mode is activated. The circuit breaker limit can be
disabled by connecting the SENSE+ and SENSE? pins together.
Positive Supply Input Pin. The ADM1170 operates between 2.7 V to 16.5 V. An undervoltage lockout (UVLO)
circuit with a glitch filter resets the ADM1170 when the supply voltage drops below the specified UVLO limit.
Rev. A | Page 5 of 16
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